As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, it will be necessary to create memory devices for which the testing of the device must be minimized in order to minimize costs. Current memory testing costs are significant and are expected to grow as the capacity of the devices grows. The cost of the testing can be estimated by dividing the annual amortized plus variable costs of the test equipment by the number of devices tested per year. The higher the memory's capacity, the more storage locations that must be tested, and the longer the testing operation will take. As memory devices enter the Gigabyte range and larger, the number of devices that a given piece of test equipment can test in a given period of time will go down. As a result, the cost per unit attributable to testing should rise. If testing is to be reduced or eliminated while maintaining high manufacturing yields, a new approach to error correcting will have to be employed.
The prior art includes many approaches for correcting errors in memory devices. This is typically accomplished by identifying faults and substituting for them. One approach to error correcting is to thoroughly test the memory device at the time of manufacture, to identify the points of failure within the device and to remap, rewire or reconfigure the device to substitute extra circuitry included in the device for the defective circuits. This can done at the time of manufacture by laser burning the wiring so as to make the circuit substitution. However, this requires that each device be thoroughly tested in order to identify the locations of the faults and this extensive testing can be very expensive, especially when the number of bytes of memory is very large. The subsequent post-manufacturing error correcting of this approach further increases the cost of the device.
Alternatively, logic can be incorporated into the device that can maintain a table of defective bit locations and dynamically substitute functioning storage bits for the bits determined to be defective, and this determination can be made during device operation. But, this requires that the spare bits, at least, be tested for proper operation and each memory must undergo self analysis before it can be used or during ongoing operation of the device. Average device density is also reduced as chip area is consumed by the fault detection and correction circuitry.
Rotating storage media, such as some magnetic disks, CD-ROM and DVD deals with this problem by including enough error correcting bits to fix a predetermined number of flawed bits. With this class of storage device, the individual data bits need not be tested for correctness because the likely worst-case number of bad bits has been calculated in advance and an error correcting algorithm (along with its necessary number of error correcting bits) is selected to ensure that this worst-case number of bad bits can be corrected. In this way, the cost of testing vast quantities of data bits can be avoided along with the associated testing costs. This approach is especially useful for storage devices that operate on data in large blocks or sectors where error correcting techniques are most efficient. Typically, as the size of a block of data increases, the number of error correcting bits increases more slowly; this results in a smaller percentage of error correcting bits as the size of the data block grows. This method of error correcting in a block of data works as long as the number of data bits does not exceed the worst-case number of bad bits.
Semiconductor memories are typically laid out as a two dimensional array having a plurality of row lines and column lines. While it is possible that any given bit in the array is flawed and inoperative, one must also worry about other failure modes. One common failure mode occurs when one of these rows or columns has a break in it thereby making a portion of the array addressed by that row or column inaccessable. Alternatively, another common failure mode occurs when a short circuit exists between adjacent rows, adjacent columns, or a row and a column thereby making it impossible to separately address bits accessed by the shorted together rows or columns. In both of these failure modes, large numbers of data bits can be inaccessible (i.e., all the bits that would be accessed by the flawed row or column). Therefore, as with the application of error correcting for CD-ROM and DVD, too many bits may be lost in a given block of bits for the error correcting algorithm and error correcting bits to be able to correct for these errors.
Presently, in some applications such as digital photography and music and video playback, to name a few, memory is so expensive that its cost often greatly exceeds the value of the data contained within it. Since data in these examples is accessed in as large blocks, CD-ROM and DVD have become popular because this media is inexpensive. However, CD-ROM and DVD are inconvenient because they are fragile and consume large amounts of power due to their lasers, motors and servo mechanisms.
What is needed is an inexpensive memory device, particularly for these large data applications that happen to access data in large blocks, for which error correcting can be implemented without having to extensively test the device at the time of manufacture and which can be effective for the expected worst case number of bad bits even if row or column line breaks or shorts exist.